The present invention relates generally to charge pumps used in phase/delay-locked loops and deals more particularly with a charge pump having a linear time to charge transformation across the rail-to-rail voltage range.
Digital frequency synthesizers have long been used in communication systems, particularly RF communications systems, to generate RF signals carried over RF channels. In frequency synthesis, it is desirable to achieve the selected frequency output with low phase noise in as little time as possible with any spurious output frequencies minimized. It is known to create a frequency synthesizer by placing a frequency divider function between the voltage-controlled oscillator (VCO) output and the phase frequency detector (PFD) in a phase-locked loop (PLL), wherein the VCO output frequency is an integer multiple of the input reference frequency to the PFD. The spurious outputs in question are usually associated with the charge pump in the PFD and occur at the phase detector operating frequency, which is generally the same as channel spacing. Incorporating the fractional-N division function in the PLL allows the phase detector to operate at a much higher frequency for the same channel spacing and have better phase noise, however, the fractional-N division function also introduces fractional spurs at the fractional offset and fractions of the comparison frequency.
A functional block diagram of a representative phase-locked loop frequency synthesizer having a frequency divider function in the feedback loop between the VCO output and the phase detector is illustrated in FIG. 1 and generally designated 10. The phase-locked loop frequency synthesizer 10 is a general class known as Integer-N phase-locked loop frequency synthesizers. A reference frequency (FIN) from a frequency generator source 12 is applied to the input 14 of a frequency reference divider 16. The reference divider 16 generates the desired reference frequency FREF at its output 18, which is coupled to one input 20 of a phase frequency detector (PFD) 22. A divide-by-N counter 50 located in the feedback path between the VCO output 48 and an input 24 of the PFD 22 provides the desired fractional division function. The PFD 22 has an UP output 26 and a DOWN output 22 coupled to the UP input 32 and DOWN input 34, respectively, of the charge pump 30 which is shown separately from the PFD 22 for purposes of clarity and to give a better understanding of the invention. The charge pump 30 responds to the UP or DOWN input signal from the PFD 22 to supply or sink current at its output 36, which output 36 is coupled to the input 38 of the loop filter 40. The output 42 of the loop filter 40 is coupled to the input 44 of the VCO 46 to provide control to the VCO to cause it to generate the desired output frequency FOUT at its output 48. The signal FCOMP at the output 54 of the divide-by-N counter 50 is coupled to the input 24 of the PFD 22 and is representative of the loop phase error, that is, the difference in phase between the frequency FOUT at the VCO output 48 and the input frequency FREF at the input 20 to the PFD 22. The operation of Integer-N phase locked loops of the general type described above wherein a charge pump sources or sinks current to or from the loop filter is well known to those skilled in the art. It will also be understood by those skilled in the art that a charge pump sources or sinks current to or from the loop filter in a similar manner in fractional-N phase locked loops. The reader 20 is referred to textbooks and readily available commercial literature to gain a fuller understanding of the operation of such PLLs.
As frequency synthesizers operate at increasingly faster or higher speeds due to the continuous advances made in semiconductor processes, which processes have provided for improved component matching and performance, there has been a need to improve the performance and linearity of charge pumps used to drive the loop filter in a phase-locked loop. One approach to improve performance has been to use a cascoded current mirror as illustrated in FIG. 2 to achieve matching at the output. By definition a linear timing error-to-voltage correction will be needed when the reference frequency FREF is compared to the divided VCO frequency FCOMP. A linear timing error-to-voltage correction is achieved by ensuring that for all voltages there is a constant current flowing into a known capacitance as in the case of the loop filter in the phase-locked loop. As semiconductor fabrication techniques improve to operate with lower voltage power sources, it is necessary to provide more output current for a given die size and to maintain precise regulation of the current. A typical prior art rail-to-rail charge pump is represented by the electrical circuit schematic diagram shown in FIG. 2 and is generally designated 100. The charge pump 100 includes cascoded current mirrors in an attempt to achieve matching for linear operation. In the rail-to-rail cascaded current mirrors circuit shown in FIG. 2, the sink and mirroring devices must be very closely matched for balancing. When switches S1 and S2 operate due to the PFD generating an UP signal, current flows from rail VDD through P1 and P4 and is mirrored in P3 and P6, respectively. Current through P3 and P6 is delivered to the VCAP NODE at the charge pump output 102 to charge or source current to the end 104 of the loop filter capacitor generally designated 106, that is, increase the voltage across the loop filter capacitor. The end 108 of the loop filter capacitor 106 opposite the VCAP NODE output 102 is connected to the rail VSS.
When switches S3 and S4 operate due to the PFD generating a DOWN signal, current flowing through N7 and N9 is mirrored in N8 and N10, respectively, to sink current from the VCAP NODE at the charge pump output 102 to discharge the loop filter capacitor 106, that is, to lower the voltage across the loop filter capacitor. When switches S3 and S4 are operated, switches S1 and S2 are open, and the current flowing through P1 and P4 is mirrored in P2 and P5, respectively. The current through P2 and P5 flows through N7 and N9 to the rail VSS.
IREF is a current source. If the sink and mirroring devices are not precisely matched, the current supplied to and sunk from the VCAP NODE at the charge pump output 102 will not have a linear response, that is, the loop filter capacitor 106 may charge and discharge at different rates from the same number of UP signal and DOWN signal pulses from the PFD. This causes the voltage at the VCAP NODE to vary over time during the charging and discharging of the loop capacitor, which results in reference spurs for integer PLLs and fractional and offset spurs for fractional PLLs and a nonlinear time-to-charge transformation.
The prior art cascoded current mirror charge pump of FIG. 2 also has limitations on the switching speed of switches S1, S2 and S3, S4 due to the characteristics of transistor devices P3, P6 and N8, N10. The transistors P3, P6 and N8, N10 are of relatively large size in the range of L=1 xcexcm and W=1000 xcexcm which causes the devices to act or function as large capacitors. Any differences in switching times between switches S1, S2 or S3, S4 cause the transistor device to discharge during the switching time interval difference, that is, one transistor is switched fully ON or OFF before the other transistor is switched fully ON or OFF. It is this discharge caused by the switching time difference that controls the maximum switching frequency of the switches. The cascoded transistors and additional transistor switch limit the range of the voltage on VCAP NODE at the charge pump output 102 due to the voltage drops across the devices.
Accordingly, it is an object of the present invention to provide a linear rail-to-rail charge pump that overcomes the disadvantages of prior art rail-to-rail charge pumps.
It is a further object of the present invention to provide a linear rail-to-rail charge pump that compensates for any differences in switching times between the UP and DOWN switching transistors.
It is a yet further object of the present invention to provide a linear rail-to-rail charge pump that uses a feedback circuit to insure a linear time to charge transfer characteristic at the charge pump output.
It is a still further object of the present invention to provide a linear rail-to-rail charge pump for use in a phase locked loop that substantially eliminates non-linearities that cause the VCO frequency output to have less than a linear frequency response.
In accordance with the invention, a charge pump having a linear time to charge transformation across the rail-to-rail voltage range is presented.
The rail-to-rail linear current mode charge pump circuit has an input source current IREF and operates between a first voltage rail VDD and a second voltage rail VSS. A first current source device is coupled to the first voltage rail VDD and is connected to a first current mirroring source device for mirroring the current through the first current source device. A first current sink device is coupled to the second voltage rail VSS and also to a first current mirroring sink device for mirroring the current through the first current sink device. The first current source device and the first current sink device are also coupled in electrical series and form a voltage node VCOMP therebetween. A first switching device having ON and OFF states and responsive to a first control signal switches between its ON and OFF states to cause the first current mirroring source device to source current to an output voltage node. A second switching device having ON and OFF states and responsive to a second control signal switches between its ON and OFF states to cause the first current mirroring sink device to sink current from the output voltage node.
A rail-to-rail feedback network is coupled between the first current source device and the first current sink device and an IREF current splitting circuit. The current splits in such a way that the current sourced to or sunk from the output voltage node is copied to the voltage node VCOMP. The voltage at the voltage node VCOMP reaches a steady state condition when the current flowing through the first current source and the first current sink devices is equal, whereby the charging or discharging of the voltage at the output voltage node is a function of the timing of the first switching device and second switching device.
Preferably, the first current source device has matching operational characteristics with the first current mirroring source device, and the first current sink device has matching operational characteristics with the first current mirroring sink device.
Preferably, the voltage at the output voltage node has a linear transfer characteristic over the voltage range between VDD-VSS.
Preferably, the UP control signal and the DOWN control signal are generated by a phase frequency detector.
Preferably, the first switching device is coupled in series with the first current mirroring source device and the output voltage node, and the second switching device is coupled in series with the first current mirroring sink device and the output voltage node.
In a further aspect of the invention, a method for providing a linear time-to-charge transformation in a rail-to-rail current mode charge pump is presented. The method includes the steps of:
providing an input source current IREF;
providing a first voltage rail VDD;
providing a second voltage rail VSS;
coupling a first current source device to the first voltage rail VDD;
mirroring the current through the first current source device in a first current mirroring source device;
sourcing current from the first current mirroring source device to an output voltage node in response to a first control signal;
coupling a first current sink device to the second voltage rail VSS;
mirroring the current through the first current sink device in a first current mirroring sink device;
sinking current from the first current mirroring sink device and from the output voltage node in response to a second control signal;
coupling the first current source device and the first current sink device in electrical series and forming a voltage node VCOMP therebetween;
coupling a rail-to-rail feedback network between the first current source device and the first current sink device for splitting the current IREF such that the current sourced to or sunk from the output voltage node is copied to the voltage node VCOMP to cause the voltage at the voltage node VCOMP to reach a steady state condition when the current flowing through the first current source and the first current sink devices is equal, whereby the charging or discharging of the voltage at the output voltage node is a function of the timing of the first switching and second switching control signals.